This invention relates generally to semiconductor manufacturing techniques, more particularly to field effect transistor manufacturing techniques.
As is known in the art, metal electrode semiconductor field effect transistors are used in monolithic microwave integrated circuits. Such circuits are employed to amplify or switch high frequency r.f. signals. The more commonly used field effect transistor in microwave circuits is the MESFET (metal electrodes semiconductor field effect transistor). A typical MESFET includes a substrate typically of a III-V material such as gallium arsenide having disposed thereover an active layer which forms a channel region between source and drain contact layers. Disposed over the contact layers are source and drain electrodes disposed in low resistivity ohmic type contact to the contact layer. The active region generally has disposed thereover a gate electrode disposed in Schottky-barrier contact to the active region. Two principal techniques are known for providing the active layers and contact layers for a MESFET. In one technique, epitaxial layers of III-V materials such as gallium arsenide are grown in sequence over a gallium arsenide substrate. A more recent technique involves so-called ion implantation in which an ion specie is directed towards selected portions of the substrate and such ions are implanted into the surface of the substrate to provide a dopant species therein. Typically, during ion implantation, lattice damage of the crystal of gallium arsenide occurs. Such damage is repaired by subjecting the implanted substrate to an elevated temperature. This is commonly referred to as annealing.
The high concentration N.sup.+ contact layers used as contact layers in the MESFET for drain and source electrode are formed by ion implanting donor ions such as silicon or selenium. The separation between the gate and the N.sup.+ implant on the source side (l.sub.SG) and between the gate and the N.sup.+ implant on the drain side (l.sub.DG) have important influences on device characteristics particularly for high power FETS. Typical, desirable values for l.sub.SG are in the range of 0&lt;l.sub.SG .ltoreq.1 .mu.m and for l.sub.DG, 0&lt;l.sub.DG .ltoreq.2 .mu.m depending upon the type of field effect transistor specifications, particularly whether the transistor will be used as a power device, switching device, a digital circuit device, or a low noise device.
Nevertheless, given a specified level of performance for the field effect transistor, accurate and precise placement of the gate electrode between the N.sup.+ implanted regions is sought. Several restrictions are imposed on registration schemes which are used during implant doping of gallium arsenide. In order that the implanted specie become electrically activated and thus properly dope the gallium arsenide crystal, the gallium arsenide crystal must be heated to the range of 800.degree.-1000.degree. C. to anneal implant induced radiation damage from the crystal and activate the dopant species. Most materials will react with or interdiffuse with gallium arsenide at these temperatures. Moreover, at these temperatures, the gallium arsenide surface will undergo dissociation (i.e. loss of arsenic). Thus, it is generally necessary to provide an implant anneal dielectric cap over the gallium arsenide substrate to prevent this loss. As a result of these limitations on processing, the implant and anneal steps are among the first steps performed in fabrication of field effect transistors. Following implant anneal, however, it is not possible to visually distinguish implanted regions from non-implanted regions or implanted regions having different dopant concentration. Therefore, there is no image to guide registration of subsequent alignment steps to the implanted and unimplanted regions of the substrate.
A straight forward registration procedure would be to form alignment marks on the wafer surface. Such alignment marks could take the form of a pattern etched into the gallium arsenide surface or into some film deposited on the surface. If such a film is used, they must be compatible with the high temperatures encountered during the annealing cycle. Moreover, subsequent layers such as the N.sup.+ implant and field effect transistor gate process must also be aligned to the same set of markers. In this case, however, the error in registration of a second layer to a first layer would be the combined error of registration of each layer to the markers. Higher accuracy is required for many applications of field effect transistors. Accordingly, a more accurate registration technique is required.